This invention relates to methods for synthesizing an integrated circuit chip as several circuit modules which are synchronized with a clock signal, and which are intercoupled by intermodule signals that are generated and processed in different modules within a single clock cycle.
In the prior art, various hardware description languages have been developed for use in synthesizing integrated circuit chips. One example of such a hardware description language is the language called Verilog. Using such a language, the functional behavior of an integrated circuit chip can be specified by an engineer; and that functional behavior can then be sent as an input to a circuit synthesizer program which in turn generates circuitry on a chip that performs the specified behavior.
With a hardware description language, the functional behavior for an entire chip can be described as a single module. However, as the number of transistors on a chip increases, describing the chip as a single module becomes impractical. Synthesizing a chip as a single module which contains over a million transistors can take several weeks to run. This problem is avoided by partitioning a chip into multiple modules which are synchronized with a clock signal, and by synthesizing each module separately.
However, when the functional behavior of a chip is partitioned into multiple modules, then a new problem inherently occurs. Due to the partitioning, a large number of intermodule signals will arise which are generated in one module and processed in one or more different modules. In a practical chip, thousands of these intermodule signals can exist; and, in order to synthesize the circuitry for any one module, timing constraints must be specified for all ports on which the intermodule signals enter or exit that module.
Since all of the modules in an actual chip together can generate and process thousands of intermodule signals, the task of specifying the timing constraints properly for all of the intermodule ports is horrendous. If the timing constraint for a port is made too small, then the synthesizer program will have to spend too much time trying to synthesize a circuit which meets the constraint; and that adds to the cost of the synthesis. Further, if a port timing constraint is too small, the synthesizer program may not be able to synthesize a circuit which meets the constraint, in which case the synthesizer program will eventually stop trying and simply report the failure.
Also, whenever the timing constraint for a first port on one module is too small, then it follows that the timing constraint for a second port on another module which is connected to the first port will be too large. This large constraint is a problem because synthesizer programs work on meeting the timing constraint of just one port at a time; and they sequentially select the port which has the worst timing constraint violation. Thus, when the timing constraint for the second port is too large, the synthesizer program will never even select the second port and try to speed up the circuitry which connects to it. Instead, the synthesizer program will only try to speed up the circuitry which connects to the first port where the timing constraint is too small. Consequently, the probability that the synthesized circuits will generate and process the intermodule signal on the first and second ports within the cycle time of the clock is greatly reduced.
Accordingly, a primary object of the present invention is to provide a novel method of fabricating an integrated circuit chip by which the above problems are overcome.